Etching Effect On The Formation Of Silicon Nanowire Transistor Patterned By AFM Lithography.

Anisotropic etching of silicon has been widely used in fabrication of MEMS devices for many years. In this work, TMAH and KOH with IPA are used to etch silicon nanowire transistor patterns

Simulation of transport in laterally gated junctionless transistors fabricated by local anodization with an atomic force microscope

In this paper, we have investigated the characteristics and transport features of junctionless lateral gate transistors via measurement and simulations. The transistor is fabricated using an atomic force microscopy (AFM) nanolithography technique on silicon-on-insulator (SOI) wafer. This work develops our previous examination of the device operation by using 3D numerical simulations to offer a better understanding of the origin of the transistor operation. We compare the experimental measurements and simulation results in the transfer characteristic and drain conductance. We also explore the behavior of the device in on and off states based on the variation of majority and minority carriers' density, electric-field components, and recombination/generation rate of carriers in the active region of the device. We show that the device is a normally on device that can force the current through a depleted region (off state) and uses bulk conduction instead of surface conduction. We also found that due to the lateral gate design, low-doped channel, and lack of the gate oxide the electrostatic squeezing of the channel effectively forces the device into the off state, but the current improvement by accumulation of carriers is not significant

Pinch-off effect in p-type double gate and single gate junctionless silicon nanowire transistor fabricated by atomic force microscopy nanolithography

The spark of aggressive scaling of transistors was started after the Moors law on prediction of device dimensions. Recently, among the several types of transistors, junctionless transistors were considered as one of the promising alternative for new generation of nanotransistors. In this work, we investigate the pinch-off effect in double gate and single gate junctionless lateral gate transistors. The transistors are fabricated on lightly doped (1015) p-type Silicon-on-insulator wafer by using an atomic force microscopy nanolithography technique. The transistors are normally on state devices and working in depletion mode. The behavior of the devices confirms the normal behavior of the junctionless transistors. The pinch-off effect appears at VG +2.0 V and VG +2.5 V for fabricated double gate and single structure, respectively. On state current is in the order of 10-9 (A) for both structures due to low doping concentration. The single gate and double gate devices exhibit an Ion/Ioff of approximately 105 and 106, respectively

Impact of KOH etching on nanostructure fabricated by local anodic oxidation method

In this letter, we investigate the impact of potassium hydroxide (KOH) etching procedure on Silicon nanostructure fabricated by Atomic force microscopy on P-type Silicon-on-insulator. An electrochemical process, as the local anodic oxidation followed by two wet chemical etching steps, KOH etching for silicon removal and hydrofluoric etching for oxide removal, were implemented to fabricate the silicon nanostructures. The effect of the pure KOH concentrations (10% to 30% wt) on the quality of the surface is studied. The influence of etching immersing time in etching of nanostructure and SOI surface are considered as well. Impact of different KOH concentrations mixed with 10% IPA with reaction temperature on etch rate is investigated. The KOH etching process is elaborately optimized by 30%wt. KOH + 10%vol. IPA in appropriate time and temperature. The angle of the walls in etch pit for extracted nanowire reveals some deviation from the standard anisotropic etching

Fabrication of p-type Double gate and Single gate Junctionless silicon nanowire transistor by Atomic force microscopy nanolithography

In this work, we have investigated the fabrication of Double gate and Single gate Junctionless silicon nanowire transistor using silicon nanowire patterned on lightly doped (105 cm-3) p-type Silicon on insulator wafer fabricated by Atomic force microscopy nanolithography technique. Local anodic oxidation followed by two wet etching steps, Potassium hydroxide etching for Silicon removal and Hydrofluoric acid etching for oxide removal, were implemented to reach the structures. Writing speed and applied tip voltage were held in 0.6 µm/s and 8 volt respectively for Cr/Pt tip. Scan speed was held in 1.0 µm/s. The etching processes were elaborately performed and optimized by 30%wt. Potassium hydroxide + 10%vol. Isopropyl alcohol in appropriate time, temperature and humidity. The structure is a gated resistor turned off based on a pinch-off effect principle, when essential positive gate voltage is applied. Negative gate voltage was unable to make significant effect on drain current to drive the device into accumulation mode

Fabrication of p-type Double gate and Single gate Junctionless silicon nanowire transistor by Atomic Force Microscopy Nanolithography

Keywords: Local anodic oxidation (LAO); Silicon-on-insulator (SOI); Atomic force microscope (AFM), Double gate (DG) and Single gate (SG) Junction-less silicon nanowire transistor (JLSNWT). Abstract. In this work, we have investigated the fabrication of Double gate and Single gate Junctionless silicon nanowire transistor using silicon nanowire patterned on lightly doped (10 5 cm -3 ) p-type Silicon on insulator wafer fabricated by Atomic force microscopy nanolithography technique. Local anodic oxidation followed by two wet etching steps, Potassium hydroxide etching for Silicon removal and Hydrofluoric acid etching for oxide removal, were implemented to reach the structures. Writing speed and applied tip voltage were held in 0.6 µm/s and 8 volt respectively for Cr/Pt tip. Scan speed was held in 1.0 µm/s. The etching processes were elaborately performed and optimized Online: 2013-01-25 ISSN: 2234-9871, Vol. 3, pp 93-113 doi:10.4028/www.scientific.net/NH.3.93 © 2013 This is an open access article under the CC-BY 4.0 license (https://creativecommons.org/licenses/by/4.0/) by 30%wt. Potassium hydroxide + 10%vol. Isopropyl alcohol in appropriate time, temperature and humidity. The structure is a gated resistor turned off based on a pinch-off effect principle, when essential positive gate voltage is applied. Negative gate voltage was unable to make significant effect on drain current to drive the device into accumulation mode. Nano Hybrid